What is the ? (e.g., FPGA, custom ASIC, mixed-signal, network processor)
While scan chains test the internal parts of a single chip, tests the connections between multiple chips on a printed circuit board (PCB).
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While simple, ad-hoc methods lack scalability and automated tool support. Structured DFT: Scan Design
By replacing standard flip-flops with "Scan Flip-Flops," engineers can daisy-chain them into a long shift register. This allows you to "shift in" a specific state and "shift out" the result. What is the
Forcing the target node to its opposite logical state (e.g., driving a to test for SA0).
┌───────┐ Normal Data (D) ─┤0 │ │ MUX ├─► [ Flip-Flop ] ──► Normal Output (Q) Scan Input (SI) ─┤1 │ │ └───┬───┘ ▼ │ To Next Scan Cell Scan Enable (SE) ────┘ This link or copies made by others cannot be deleted
The you are working with (e.g., ASICs, FPGAs, or SoCs)
Measuring the steady-state supply current. A high current draw in a CMOS circuit often indicates a bridge or short, even if the logic appears to function correctly. Finding the Right "Solution"
Test patterns are shifted into the scan chain bit-by-bit (high controllability).